1. Field of the Invention
The present invention relates to a programmable controller which executes a basic instruction primarily for bit operations and an application instruction for processing data comprising a plurality of bits and, more particularly, to a programmable controller equipped with hardware (a processor) specifically designed so as to be able to process both the basic and application instructions.
2. Related Art
Programmable controllers are widely used in the control of industrial apparatus, machines, and factory automation equipment. There has been a demand for higher-speed processing of a larger number of input/output signals associated with the increased complexity of an object apparatus and a demand for higher-speed operations. For this reason, high-speed processing is implemented by hardware (a processor) specifically designed so as to be able to process a basic instruction primarily for bit operations and an application instruction for processing data which comprises a plurality of bits. A programmable controller is constructed by combination of the hardware and a general-purpose microprocessor which carries out communication processing and peripheral processing.
That specifically designed hardware (i.e., processor) of a conventional example has a three-stage pipeline structure, and an instruction is executed through this pipeline structure. In this case, processing executed in the execution stage comprises the following details.
First Stage
Instruction fetch for fetching an instruction to be subsequently executed from instruction
Second Stage
Various arithmetic and logic operations, data address calculations for calculating an address of data memory, or target branch operation processing following instruction decode and register fetch processing
Third Stage
Memory access processing (i.e., read/write processing) for carrying out reading/writing operations with respect to the data memory, branching operations, bit operations, or writing operations with respect to the general-purpose register.
In the pipeline structure, the overall speed of execution of instructions depends on a processing rate of the slowest instruction execution stage among all the stages. To speed up such pipeline processing, it is necessary to provide each instruction execution stage with uniform speed. However, in the previously described three-stage pipeline structure, if memory which takes the same access time is used for the instruction memory and the data memory, the overall speed of execution becomes slower and a much longer processing time is required, because the second or third stage carries out processing such as a bit operation which takes a much longer processing time than the processing executed in the first stage.